Double gate semiconductor device structures are promising candidates for future generation microelectronics devices, because of the ability to obtain near ideal sub-threshold slope, absence of body-effect, immunity to short-channel effect, and very high current driveability. One double gate device structure of technological relevance is the FinFET. The FinFET is particularly attractive because of the relative simplicity of manufacture compared to other double gate devices. The channel for the FinFET is a thin rectangular island of Si, commonly referred to as the Fin. The gate wraps around the Fin so that the channel is gated on both sides of the vertical portions of the Fin structure, providing gate control which is superior to planar single gate MOSFETs.
FinFETs are well known. See, for example, U.S. Pat. No. 6,413,802, entitled “FinFET Transistor Structures Having a Double Gate Channel Extending Vertically from a Substrate and Methods of Manufacture” by Hu et al., filed Oct. 23, 2000, issued Jul. 2, 2002, which is hereby incorporated in its entirety by reference. FinFETs having enhanced mobility are also known. See, for example, U.S. Patent Application No. 2002/0063292 A1, entitled “CMOS Fabrication Process Utilizing Special Transistor Orientation” by Armstrong et al., filed Nov. 29, 2000, published May 30, 2002, which is hereby incorporated in its entirety by reference. This prior art method is directed at improving nFET mobility and, therefor, only limited improvement in CMOS circuits can be attained. Thus, a need exists for a method to improve mobility for p-FinFETs and n-FinFETs which are situated on the same wafer.
However, the present inventors believe that improvements in utilizing stressing layers to enhance mobility are achievable.